Part Process Description Application, features PDF
8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers
Number of masks, pcs.                                           26
Design rule,µm                                                     0.8
Substrate:                           Si/B-doped/ p-type/Res 3
Epitaxy:                 Si/P-doped/ n-type/ Thk 2.4/ Res 4.5
p-well depth with p+cc, µm                                   4.3
n-well depth with n+cc, µm                                   4.3
Gate SiO2, Å                                                        130
Interlayer dielectric:                                         BPSG
Interlevel dielectric:                           PEoxide+ SOG
NMOS/PMOS channel length, µm                 0.9/1.0
N&P LDD- drains
Me I                                               Ti-TiN/Al-Si/TiN
Me II                                                      Ti/Al-Si/TiN
NPN emitter size, µm                                    1.2*3.2
Space line PolySi 2,µm                                       1.8
Contacts 1, µm                                                  Ø 0.9
Space line Me 1, µm                                             2.2
Contacts 2,µm                                                  Ø 0.9

Space line Me 2, µm                                             2.4

Analogue-digital  IC for TV-receivers, Ucc=8V
 
NMOS: Vtn=0.6 V, Usd >12 V
PMOS: Vtр=-0.9 V, Usd >12 V
NPN vertical:
bn =120    Uce=10 V
PNP lateral:
bp =45      Uce=13 V
200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors
Number of masks, pcs.                                            19
Min design rule,µm                                             4.0
Substrate:        Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)
Buried layers:            Si/Sb-doped/ n-type/Thk 30/Res 5.5;
                                  Si/B-doped/ p-type/Thk 300/Res2.0 ; 
Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0;
Isolation:                                                    p-n junction
P-well depth, µm                                                      6.5
NDMOS base depth, µm                                          3.0
Gate SiO2, Å                                                           900
NPN p-base depth, µm                                             2.5
N+emitter depth, µm                                                0.8
Interlayer dielectric –  medium temp. PSG
0,55mm +SIPOS 0.1µm + medium temp. PSG    1,1µm
Channel length (gate):
N/PDMOS, µm                                                            6                                            
Space line PolySi, µm                                                 8
Contacts, µm                                                             Ø4

Space line Me, µm                                                      12

Small -scale integration analogue IC, 
VDD <  210 V
 
NPN Vertical:
bn =70 Uсе=50 V
NDMOS: Vtn= 2.0 V,
Usd >200 V
PDMOS: Vtp= -1.0 V,
Usd >200 V
NMOS: Vtn= 1.5V, Usd >20V
 
Resistors in layer:
NPN base, Р-drain, PolySi.
 
Capacitors: PolySi-Si (SiO2 900 Å)

PolySi-Al (SiO2 1600 Å)

BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me
Number of masks, pcs.                                               16
Min design rule,µm                                                      3.0
Substrate:            Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)
Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;
                                       Si/B-doped/ p-type/Thk 250/Res2.0
Epi layer:                      Si/P-doped/ n-type/ Thk 12/ Res 1.5;
Isolation:                                                         p-n junction
P-well depth, µm                                                          5.0
Gate SiO2, Å                                                                750
Interlayer dielectric – Medium temp. PSG, µm       0,8
Power electronics actuator  IC
NPN Vertical:
h21E=25-90 Uсе=20-70 V
PNP Lateral:
h21E=2,2-30 Uсе=25-60 V
NDMOS: Vtn=1.8-2.6В, Usd=60-100 V
Low voltage PMOS:
Vtp=0.8-1.4 V, Usd =20-35 V
High voltage PMOS:
Vtp=1.2-2.2 V, Usd =30-80 V
NMOS  transistor:

Vtn=1.1-1.7 V, Usd =15-25 V

BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me
Number of masks, pcs.                                              15
Min design rule,µm                                                     3.0
Substrate:           Si/B-doped/ p-type/ Thk 460/ Res 60/ (100)
Isolation:                                                        p-n junction
NDMOS base depth, µm                                             2.5
Gate SiO2, Å                                                                 750
Interlayer dielectric – medium temp. PSG, µm       0,8
SMPS-IC  
Low voltage NPN:
h21E   50 min, Uсе 30V min
PNP Lateral:
h21E=2,2-30 Uсе=25-60 V
NDMOS: Vtn=1.2-3.0 V,  Usd >=30 V
Low voltage PMOS:
Vtp=0.8-2.0 V, Usd  >=18 V
High voltage PMOS:
Vtp=0.8-2.0 V, Usd  >=22 V
Low voltage NMOS:
Vtn=0.8-2.0 V, Usd  >=18 V
High voltage NMOS:

Vtn=0.8-2.0 V, Usd  >=600 V

90 V, p-n junction isolation, 1 PolySi, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors
Numberofmasks, pcs.                                             19
Min design rule,µm                                              4.0
Substrate:          Si/B-doped/  p-type/ Thk 460/ Res 12/ (100)
Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;
                                      Si/B-doped/ p-type/Thk 250/Res2.0 ;
Epi layer:                     Si/P-doped/ n-type/ Thk 10/ Res 1.5;
Isolation:                                                    p-n junction
P-well depth, µm                                                     6.5
NDMOS base depth, µm                                         2.5
Gate SiO2, Å                                                          750
NPN p-base depth, µm                                            2.5
N+emitter depth, µm                                               0.5
Interlayer dielectric - BPSG, µm                             0,8                                           
Channel length (gate):
N/PMOS, µm                                                         Ø 4
Space line PolySi, µm                                                7
Contacts, µm                                                              2

Space line Me, µm                                                     8

Small and medium-scale integration analogue IC, VDD <  90 V
NPN Vertical:
bn =50 Uсе=20 V
PNP Lateral:
bр =25 Uсе=20 V
LNDMOS: Vtn= 2.0 V, Usd >90 V
LPDMOS: Vtp= -1.4 V, Usd >90 V
NMOS: Vtn= 1.2 V, Usd >18 V
PMOS: Vtp= 1.5 V, Usd >18 V
VNDMOS: Vtn= 2.0 V, Usd >70 V
 
Resistors in layer:
NDMOS base, Р-drain, PolySi.
Capacitors: PolySi-Si (SiO2 750Å)

PolySi-Al (SiO2 8000 Å)

BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors
Number of masks, pcs.                                             15
Min design rule,µm                                             2.8
Substrate:                                   Si/B-doped/ p-type/ Res 80
Isolation:                                                                   LOCOS
P-well depth, µm                                                     6.5
N-well depth, µm                                                     4.5
NDMOS base depth, µm                                         2.4
Gate SiO2, Å                                                           600
Interlayer dielectric – Medium temp. PSG, µm       0,6                           
Channel length (gate): N/PMOS, µm                     2.0
Contacts, µm                                                    2.0x2.0
Space line Me 1, µm                                                 8
Space line Me 2, µm                                                10
Low-voltage transistors:
NMOS: Vtn= 1.8 V, Usd >16 V
PMOS: Vtp= 1.5 V, Usd >16 V
NPN: h21e= 100-300
Resistors in layer:
PolySi 1= 20-30 Ohm/sq
 
High-voltage transistors :
NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V
PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V